View STA335W_8324757.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

august 2009 rev 1 1/43 3 STA335W 2.0-channel high-effici ency digital audio system features wide voltage supply range ? 5 v to 26 v (operating range) ? 30 v (absolute maximum rating) 2 channels of ternary pwm (stereo mode) (2 x 20 w into 8 at 18 v) 2.0 channels of 24-bit ffx 100 db snr and dynamic range selectable 32 to 192 khz input sample rates i 2 c control with selectable device address digital gain/attenuation +48 db to -80 db with 0.5 db/step resolution soft volume update with programmable ratio individual channel and master gain/attenuation individual channel and master soft/hard mute automatic zero-detect mute automatic invalid input-detect mute 2-channel i 2 s input data interface advanced am interference frequency switching and noise suppression modes selectable high- or low-bandwidth noise-shaping topologies variable max power correction for lower full-power thd selectable clock input ratio 96 khz internal processing sample rate, 24 to 28-bit precision thermal overload and short-circuit protection embedded video apps: 576 x fs input mode supported fully compatible with sta335bw (on the common registers). powersso-36 (slug down) table 1. device summary order code package packaging STA335W powersso-36 slug down tube STA335W13tr powersso-36 slug down tape and reel www.st.com
STA335W 2/43
STA335W 3/43
description ffx STA335W 4/43 1 description ffx the STA335W is an integrated solution of digital audio processing, digital amplifier control, and ffx -power output stage, thereby creating a high-power single-chip ffx solution comprising high-quality, high-efficiency, all digital amplification. STA335W is based on ffx (full flexible amplification) processor. the STA335W is part of the sound terminal tm family that provides full digital audio streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment. the STA335W power section consists of two full-bridges. the two channels can provide up to 2 x 20 w of power. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. two channels of ffx processing are provided. this high-quality conversion from pcm audio to ffx pwm switching waveform provides over 100 db snr and dynamic range. 1.1 block diagram figure 1. block diagram protection current/thermal logic regulators bias power control ffx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital dsp i 2 c
STA335W pin connections 5/43 2 pin connections 2.1 connection diagram figure 2. pin connection powersso-36 (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig nc nc gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd config nc nc d05au1638 table 2. pin description pin type name description 1 gnd gnd_sub substrate ground 2i sa i 2 c select address (pull-down) 3 i test_mode this pin must be connected to ground (pull-down) 4 i/o vss internal reference at vcc-3.3 v 5 i/o vcc_reg internal vcc reference 6 o out2b output half bridge 2b 7 gnd gnd2 power negative supply 8 power vcc2 power positive supply 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b
pin connections STA335W 6/43 11 power vcc1 power positive supply 12 gnd gnd1 power negative supply 13 o out1a output half bridge 1a 14 gnd gnd_reg internal ground reference 15 power vdd internal 3.3 v reference voltage 16 i config paralleled mode command 17 o n.c. not to be connected 18 o n.c. not to be connected 19 o n.c. not to be connected 20 i/o n.c. not to be connected 21 power vdd_dig digital supply voltage 22 gnd gnd_dig digital ground 23 i pwrdn power down (pull-up) 24 power vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 gnd gnd_pll negative supply for pll 27 i xti pll input clock 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left/right clock 30 i sdi i 2 s serial data channels 1 and 2 31 i reset reset (pull-up) 32 o int_line fault interrupt 33 i/o sda i 2 c serial data 34 i scl i 2 c serial clock 35 gnd gnd_dig digital ground 36 power vdd_dig digital supply voltage table 2. pin description (continued) pin type name description
STA335W electrical specifications 7/43 3 electrical specifications 3.1 absolute maximum ratings warning: stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). in this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. 3.2 thermal data table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) -0.3 30 v vdd_dig digital supply voltage -0.3 4 v vdd_pll pll supply voltage -0.3 4 t op operating junction temperature -20 150 c t stg storage temperature -40 150 c table 4. thermal data parameter min typ max unit r th j-case thermal resistance junction-case (thermal pad) 1.5 c/w t th-sdj thermal shut-down junction temperature 150 c t th-w thermal warning temperature 130 c t th-sdh thermal shut-down hysteresis 20 c r th j-amb thermal resistance junction-ambient (1) 1. see section 7: package thermal characteristics on page 39 for details.
electrical specifications STA335W 8/43 3.3 recommended operating conditions 3.4 electrical specifications for the digital section table 5. recommended operating condition symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) 5 26 v vdd_dig digital supply voltage 2.7 3.3 3.6 v vdd_pll pll supply voltage 2.7 3.3 3.6 v t amb ambient temperature -20 70 c table 6. electrical specifications - digital section symbol parameter conditions min typ max unit i il low level input current without pull-up/down device vi = 0 v 1 10 a i ih high level input current without pull-up/down device vi = vdd_dig = 3.6 v 110a v il low level input voltage 0.2 * vdd_dig v v ih high level input voltage 0.8 * vdd_dig v v ol low level output voltage iol=2 ma 0.4 * vdd_dig v v oh high level output voltage ioh=2 ma 0.8 * vdd_dig v i pu pull-up/down current 25 66 125 a r pu equivalent pull-up/down resistance 50 k
STA335W electrical specifications 9/43 3.5 electrical specificatio ns for the power section the specifications given in this section are valid for the operating conditions: v cc =18v, f=1khz, f sw = 384 khz, t amb = 25 c and r l = 8 , unless otherwise specified. table 7. electrical specifications - power section symbol parameter conditions min typ max unit po output power btl thd = 1% 16 w thd = 10% 20 r dson power pchannel/nchannel mosfet (total bridge) l d = 1.5 a 180 250 m gp power pchannel rdson matching l d = 1.5 a 95 % gn power nchannel rdson matching l d = 1.5 a 95 % idss power pchannel/nchannel leakage vcc = 20 v 10 a i ldt low current dead time (static) resistive load (1) 8 15 ns i hdt high current dead time (dynamic) i load = 1.5 a (1) 15 30 ns t r rise time resistive load (1) 10 18 ns t f fall time resistive load (1) 10 18 ns v cc supply voltage operating voltage 5 26 v i vcc supply current from vcc in power down pwrdn = 0 0.1 1 ma supply current from vcc in operation pcm input signal = - 60 dbfs, switching frequency = 384 khz, no lc filters 52 60 ma i vdd supply current ffx processing (reference only) internal clock = 49.152 mhz 55 70 ma ilim overcurrent limit (2) 3.0 3.8 a isc short circuit protection hi-z output 4.0 4.2 a uvl under voltage protection 3.5 4.3 v t min output minimum pulse width no load 20 30 60 ns dr dynamic range 100 db snr signal to noise ratio, ternary mode a-weighted 100 db signal to noise ratio binary mode 90 db pssr power supply rejection ratio ffx stereo mode, <5 khz v ripple = 1 v rms audio input = dither only 80 db thd+n total harmonic distortion + noise ffx stereo mode, po = 1 w f=1khz 0.2 %
electrical specifications STA335W 10/43 x ta l k crosstalk ffx stereo mode, <5 khz one channel driven at 1 w other channel measured 80 db peak efficiency, ffx mode po = 2 x 20 w into 8 90 % peak efficiency,binary modes po = 2 x 9 w into 4 + 1 x 20 w into 8 87 1. refer to figure 5: test circuit 1 . 2. limit current if the register (ocrb par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. when disabled refer to the isc. table 7. electrical specifications - power section (continued) symbol parameter conditions min typ max unit
STA335W electrical specifications 11/43 3.6 power on/off sequence figure 3. power-on sequence note: clock stable means: f max - f min < 1 mhz note: see chapter 5.2.3: serial data first bit , for additional info. figure 4. power-off sequence for pop-free turn-off don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care note: no specific vcc and vdd_dig turn ? on sequence is required tr = minimum time between xti master clock stable and reset removal: 1 msec tc = minimum time between reset removal and i 2 c program, sequence start: 1msec don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care note: no specific vcc and vdd_dig turn ? off sequence is required
electrical specifications STA335W 12/43 3.7 testing 3.7.1 functional pin definition figure 5. test circuit 1 figure 6. test circuit 2 table 8. functional pin definition pin name number logic value ic status pwrdn 23 0 low consumption 1 normal operation twarn 20 0 a temperature warning is indicated by the external power stage 1 normal operation eapd 19 0 low consumption for power stage all internal regulators are switched off 1 normal operation dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy m58 m57 outxy gnd vdc = vcc/2 v67 r 8 + - high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=4 q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=1.5a iout=1.5a q4 q1 q3 m64 inb m63 d06au1651 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in fi g ure l68 10 l67 10 outa
STA335W i 2 c bus specification 13/43 4 i 2 c bus specification the STA335W supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. STA335W is always a slave device in all of its communications. it supports up to 400 kb/s rate (fast-mode bit rate). STA335W i 2 c is a slave only interface. 4.1 communication protocol 4.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 4.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 4.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA335W and the bus master. 4.1.4 data input during the data input the STA335W samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 4.2 device addressing to start communication between the master and the STA335W, the master must initiate with a start condition. following this, the master sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode. the seven most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA335W the i 2 c interface has two device addresses depending on the sa port configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the eighth bit (lsb) identifies read or write operation rw, this bit is set to 1 in read mode and to 0 for write mode. after a start condition the STA335W identifies on the bus the device address and if a match is found, it acknowledges the identification on sda bus during the 9th bit time. the byte following the device identification byte is the internal space address.
i 2 c bus specification STA335W 14/43 4.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA335W acknowledges this and the writes for the byte of internal address. after receiving the internal byte address the STA335W again responds with an acknowledgement. 4.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the STA335W. the master then terminates the transfer by generating a stop condition. 4.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. 4.4 read operation 4.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA335W acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 4.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the STA335W. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 4.4.3 random ad dress byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA335W acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the STA335W again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA335W acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 4.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the STA335W. the master acknowledges each data byte read and then generates a stop condition terminating the transfer.
STA335W i 2 c bus specification 15/43 4.4.5 write mode sequence figure 7. write mode sequence 4.4.6 read mode sequence figure 8. read mode sequence dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high
register description STA335W 16/43 5 register description table 9. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im reserved saifb sai3 sai2 sai1 sai0 0x02 confc ocrb csz3 csz2 csz1 csz0 om1 om0 0x03 confd reserved zde reserved reserved psl reserved reserved reserved 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide reserved reserved 0x06 mute/loc reserved reserved reserved reserved reserved c2m c1m mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0a reserved 0x0b auto1 reserved reserved reserved reserved reserved reserved reserved reserved 0x0c auto2 reserved reserved reserved reserved amam2 amam1 amam0 amame 0x0d reserved 0x0e c1cfg reserved reserved reserved reserved c1bo reserved reserved reserved 0x0f c2cfg reserved reserved reserved reserved c2bo reserved reserved reserved 0x10 reserved 0x11 reserved 0x12 reserved 0x13 reserved 0x14 reserved 0x15 reserved 0x16 cfaddr reserved reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved
STA335W register description 17/43 5.1 configuration register a (addr 0x00) 0x20 reserved 0x21 reserved 0x22 reserved 0x23 reserved 0x24 reserved 0x25 reserved 0x26 cfud reserved reserved r1 reserved w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x2a dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul fault uvfault ovfault ocfault ocwarn tfault twarn 0x2e reserved reserved ro1bact r5bact r4bact r3bact r2bact r1bact 0x2f reserved reserved r01bend r5bend r4bend r3bend r2bend r1bend 0x30 reserved reserved r5bbad r4bbad r3bbad r2bbad r1bbad 0x31 eqcfg xob reserved reserved amgc3 amgc2 reserved sel1 sel0 0x32 reserved 0x33 reserved 0x34 reserved 0x35 reserved 0x36 reserved 0x37 reserved reserved svupe svup[4] svup[3] svup[2] svup[1] svup[0] 0x38 reserved reserved svdwe svdw[4] svdw[3] svdw[2] svdw[1] svdw[0] table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011
register description STA335W 18/43 5.1.1 master clock select the STA335W supports sample rates of 32 kh z, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: 32.768 mhz for 32 khz 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. table 10. master clock select bit r/w rst name description 0r/w 1 mcs0 selects the ratio between the input i 2 s sample frequency and the input clock. 1r/w 1 mcs1 2r/w 0 mcs2 table 11. input sampling rates input sample rate fs (khz) ir mcs[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 na 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 1x na 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
STA335W register description 19/43 5.1.2 interpolation ratio select the STA335W has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consis tent. the first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. 5.1.3 thermal warning recovery bypass if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery determines if the -3 db output limit is removed when thermal warning is negative. if twrb = 0 and twab = 0, then when a thermal warning disappears the -3 db output limit is removed and the gain is added back to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears the -3 db output limit remains until twrb is changed to zero or the device is reset. 5.1.4 thermal warning adjustment bypass the on-chip STA335W power output block provides feedback to the digital controller using inputs to the power control block. input twarn is used to indicate a thermal warning table 12. internal interpolation ratio bit r/w rst name description 4:3 r/w 00 ir [1:0] selects internal interpolation ratio based on input i 2 s sample frequency table 13. ir bit settings as a function of input sample rate input sample rate fs (khz) ir 1st stage interpolation ratio 32 00 2 times oversampling 44.1 00 2 times oversampling 48 00 2 times oversampling 88.2 01 pass-through 96 01 pass-through 176.4 10 2 times downsampling 192 10 2 times downsampling table 14. thermal warning recovery bypass bit r/w rst name description 5r/w 1 twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled table 15. thermal warning adjustment bypass bit r/w rst name description 6r/w 1 twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled
register description STA335W 20/43 condition. when twarn is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 db output limit (determined by twocl in the coefficient ram) to the modulation limit in an attempt to eliminate the thermal warning condition. once the thermal warning output limit adjustment is ap plied, it remains in this state until reset, unless fdrb = 0. 5.1.5 fault detect recovery bypass the on-chip STA335W power output block provides feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either over-current or thermal). when fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (fdrc registers 0x29-0x2a), then toggles it back to 1. this sequence is repeated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. 5.2 configuration register b (addr 0x01) 5.2.1 serial audio i nput interface format table 16. fault detect recovery bypass bit r/w rst name description 7r/w 0 fdrb 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 10000000 table 17. serial audio input interface bit r/w rst name description 0 r/w 0 sai0 determines the interface format of the input serial digital audio interface. 1 r/w 0 sai1 2 r/w 0 sai2 3 r/w 0 sai3
STA335W register description 21/43 5.2.2 serial data interface the STA335W audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA335W always acts as slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data 1 and 2 sdi12. the sai bits (d3 to d0) and the saifb bit (d4) are used to specify the serial data format. the default serial data format is i 2 s, msb-first. available formats are shown in the tables and figure that follow. 5.2.3 serial data first bit table 18. serial data first bit saifb format 0 msb-first 1 lsb-first table 19. support serial audio input formats for msb-first (saifb = 0) bicki sai [3:0] saifb interface format 32 * fs 0000 0 i 2 s 15-bit data 0001 0 left/right-justified 16-bit data 48 * fs 0000 0 i 2 s 16 to 23-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data 64 * fs 0000 0 i 2 s 16 to 24-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data
register description STA335W 22/43 to make the STA335W work properly, the serial audio interface lrcki clock must be synchronous to the pll output clock. it means that: the frequency of pll clock / fre quency of lrcki = n 4 cycles, where n depends on the settings in table 13 on page 19 the pll must be locked. if these two conditions are not met, and ide bit (reg 0x05 bit 2) is set to 1, the STA335W will immediately mute the i 2 s pcm data out (provided to the pr ocessing block) and it will freeze any active processing task. to avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into STA335W data path before the desynchronization event table 20. supported serial audio input formats for lsb-first (saifb = 1) bicki sai [3:0] saifb interface format 32 * fs 1100 1 i 2 s 15-bit data 1110 1 left/right-justified 16-bit data 48 * fs 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data 64 * fs 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data
STA335W register description 23/43 happens. at the same time any processing related to the i 2 c configuration should be issued only after the serial audio interface and the internal pll are synchronous again. note: any mute or volume change causes some delay in the completion of the i 2 c operation due to the soft volume feature. the soft volume phase change must be finished before any clock desynchronization. 5.2.4 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexib ility in processi ng. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 21. channel input mapping bit r/w rst name description 6r/w 0 c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7r/w 1 c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input
register description STA335W 24/43 5.3 configuration register c (addr 0x02) 5.3.1 ffx power output mode the ffx power output mode selects how the ffx output timing is configured. different power devices use different output modes. 5.3.2 ffx compensating pul se size register table 6: d7 d6 d5 d4 d3 d2 d1 d0 ocrb csz3 csz2 csz1 csz0 om1 om0 1 011111 table 22. ffx power output mode bit r/w rst name description 0r/w 1 om0 selects configuration of ffx output. 1r/w 1 om1 table 23. output modes om[1,0] output stage mode 00 drop compensation 01 discrete output stage - tapered compensation 10 full power mode 11 variable drop compensation (cszx bits) table 24. ffx compensating pulse size bits bit r/w rst name description 2r/w 1 csz0 when om[1,0] = 11, this register determines the size of the ffx compensating pulse from 0 clock ticks to 15 clock periods. 3r/w 1 csz1 4r/w 1 csz2 5r/w 0 csz3 table 25. compensating pulse size csz[3:0] compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size ?? 1111 300 ns (15 tick) clock period compensating pulse size
STA335W register description 25/43 5.3.3 over-current warning detect adjustment bypass the ocwarn input is used to indicate an over-current warning condition. when ocwarn is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 db) in an attempt to eliminate the over-current warning condition. once the over-current warning volume adjustment is app lied, it remains in this state until reset is applied. the level of adjustment can be changed via the twocl (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient ram. 5.4 configuration register d (addr 0x03) 5.4.1 post-scale link post-scale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. 5.4.2 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 5.5 configuration register e (addr 0x04) table 26. over-current warning bypass bit r/w rst name description 7 r/w 1 ocrb 0: over-current warning adjustment enabled 1: over-current warning adjustment disabled d7 d6 d5 d4 d3 d2 d1 d0 reserved zde reserved reserved psl reserved reserved reserved 01000000 table 27. post-scale link bit r/w rst name description 3 r/w 0 psl 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value table 28. zero-detect mute enable bit r/w rst name description 6 r/w 1 zde setting of 1 enables the automatic zero-detect mute d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv
register description STA335W 26/43 5.5.1 max power correction variable 5.5.2 max power correction setting the mpc bit turns on special processing that corrects the STA335W power device at high power. this mode should lower the thd+n of a full ffx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1,0] = 01) and binary. when ocfg = 00, mpc will not effect channels 3 and 4, the line- out channels. 5.5.3 noise-shaper bandwidth selection 5.5.4 am mode enable STA335W features affx processing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ffx is operating in a device with an am tuner active. the snr of the ffx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. 11000010 d7 d6 d5 d4 d3 d2 d1 d0 table 29. max power correction variable bit r/w rst name description 0r/w 0 mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 30. max power correction bit r/w rst name description 1r/w 1 mpc setting of 1 enables power bridge correction for thd reduction near maximum power output. table 31. noise-shaper bandwidth selection bit r/w rst name description 2 r/w 0 nsbw 1: third order ns 0: fourth order ns table 32. am mode enable bit r/w rst name description 3r/w 0 ame 0: normal ffx operation. 1: am reduction mode ffx operation
STA335W register description 27/43 5.5.5 pwm speed mode 5.5.6 distortion compe nsation variable enable 5.5.7 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. 5.5.8 soft volume update enable 5.6 configuration register f (addr 0x05) table 33. pwm speed mode bit r/w rst name description 4r/w 0 pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels table 34. distortion compensation variable enable bit r/w rst name description 5r/w 0 dccv 0: use preset dc coefficient 1: use dcc coefficient table 35. zero-crossing volume enable bit r/w rst name description 6r/w 1 zce 1: volume adjustments only occur at digital zero- crossings 0: volume adjustments occur immediately table 36. soft volume update enable bit r/w rst name description 7r/w 1 sve 1: volume adjustments ramp according to svr settings 0: volume adjustments occur immediately d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide reserved reserved 01011100
register description STA335W 28/43 5.6.1 invalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and automatically mutes if the signals are perceived as invalid. 5.6.2 binary output mode clock loss detection detects loss of input mclk in bina ry mode and will outpu t 50% duty cycle. 5.6.3 lrck double trigger protection actively prevents double trigger of lrclk. 5.6.4 auto eapd on clock loss when active, issues a power device power down signal (eapd) on clock loss detection. 5.6.5 ic power down the pwdn register is used to place the ic in a low-power state. when pwdn is written as 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power-stage, then the master clock to all internal hardware expect the i 2 c block is gated. this places the ic in a very low power consumption state. table 37. invalid input detect mute enable bit r/w rst name description 2r/w 1 ide setting of 1 enables the automatic invalid input detect mute table 38. binary output mode clock loss detection bit r/w rst name description 3 r/w 1 bcle binary output mode clock loss detection enable table 39. lrck double trigger protection bit r/w rst name description 4 r/w 1 ldte lrclk double trigger protection enable table 40. auto eapd on clock loss bit r/w rst name description 5 r/w 0 ecle auto eapd on clock loss table 41. ic power down bit r/w rst name description 6r/w 1 pwdn 0: ic power down low-power condition 1: ic normal operation
STA335W register description 29/43 5.6.6 amplifier power down the eapd register directly disables/enables the internal power circuitry. when eapd = 0, the internal power section is placed on a low-power state (disabled). 5.7 volume control regi sters (addr 0x06 - 0x0a) 5.7.1 mute/line output configuration register line output is only active when ocfg = 00. in this case loc determines the line output configuration. the source of the line output is always the channel 1 and 2 inputs. 5.7.2 master volume register 5.7.3 channel 1 volume 5.7.4 channel 2 volume table 42. external amplifier power down bit r/w rst name description 7 r/w 0 eapd 0: power stage power down active 1: normal operation d7 d6 d5 d4 d3 d2 d1 d0 loc1 loc0 reserved reserved c3m c2m c1m mmute 00000000 table 43. line output configuration loc[1:0] line output configuration 00 line output fixed - no volume, no eq 01 line output variable - ch3 volume effects line output, no eq 10 line output variable with eq - ch3 volume effects line output d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000
register description STA335W 30/43 the volume structure of the STA335W consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. the individual channel volumes are adjustable in 0.5 db steps from +48 db to - 80 db. as an example if c1v = 0x00 or +48 db and mv = 0x18 or -12 db, then the total gain for channel 1 = +36 db. the master mute, when set to 1, mutes all channels at once, whereas the individual channel mutes (cxm) mutes only that channel. both the master mute and the channel mutes provide a ?soft mute? with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard (instantaneous) mute? can be obtained by programming a value of 0xff (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register any channel whose total volume is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 ( configuration register e (addr 0x04) on page 25 ) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates occur immediately. table 44. master volume offset as a function of mv[7:0] mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) hard master mute table 45. channel volume as a function of cxv[7:0] cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01011111 (0x5f) +0.5 db 01100000 (0x60) 0 db 01100001 (0x61) -0.5 db ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db
STA335W register description 31/43 5.8 audio preset registers (0x0c) 5.8.1 audio preset r egister 2 (addr 0x0c) 5.8.2 am interference frequency switching 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute table 45. channel volume as a function of cxv[7:0] (continued) cxv[7:0] volume d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 table 46. am interference frequency switching bits bit r/w rst name description 0 r/w 0 amame audio preset am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings table 47. audio preset am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz
register description STA335W 32/43 5.9 user-defined coefficient cont rol registers (addr 0x16 - 0x26) 5.9.1 coefficient address register 5.9.2 coefficient data register bits 23:16 5.9.3 coefficient data register bits 15:8 5.9.4 coefficient data register bits 7:0 5.9.5 coefficient write /read control register coefficients for user-defined scaling are handled internally in the STA335W via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. one cont ains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from ram. note: the read and write operation on ram coefficients works only if lrcki (pin 29) is switching. reading a coefficient from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write 1 to r1 bit in i 2 c address 0x26. 4. read top 8-bits of coefficient in i 2 c address 0x17. 5. read middle 8-bits of coefficient in i 2 c address 0x18. 6. read bottom 8-bits of coefficient in i 2 c address 0x19. d7 d6 d5 d4 d3 d2 d1 d0 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved r1 reserved w1 0 0000
STA335W register description 33/43 writing a single coefficient to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6-bits of address to i 2 c register 0x16. 3. write top 8-bits of coefficient in i 2 c address 0x17. 4. write middle 8-bits of coefficient in i 2 c address 0x18. 5. write bottom 8-bits of coefficient in i 2 c address 0x19. 6. write 1 to w1 bit in i 2 c address 0x26. 5.9.6 post-scale the STA335W provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. this post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass-management. this post-scale factor can be used in conjunction with an adc equipped micro-controller to perform power-supply error correction. all channels can use the channel-1 post-scale factor by setting the post-scale link bit. by default, all post-scale factors are set to 0x7fffff. when line output is being used, channel-3 post-scale will affe ct both channels 3 and 4. 5.9.7 over-current post-scale the STA335W provides a simple mechanism for reacting to over-current detection in the power-block. when the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. the default setting provides 3 db of output attenuation when ocwarn is asserted. the amount of attenuation to be applied in this situation can be adjusted by modifying the over-current post-scale value. as with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. by default, the over-current post-scale factor is set to 0x5a9df7 . once the over-current attenuation is applied, it remains unt il the device is reset. 5.10 variable max power correction registers (addr 0x27 - 0x28) table 48. ram block for scaling management index (decimal) index (hex) coefficient default 0 reserved ?? reserved 52 0x34 channel 1 - post-scale c1psts 0x7fffff 53 0x35 channel 2 - post-scale c2psts 0x7fffff 54 0x36 reserved 55 0x37 twarn/oc - limit twocl 0x5a9df7 d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8
register description STA335W 34/43 mpcc bits determine the 16 msbs of the mpc comp ensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 5.11 variable distortion compen sation registers (addr 0x29 - 0x2a) dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 5.12 fault detect recovery consta nt registers (addr 0x2b - 0x2c) fdrc bits specify the 16-bit faul t detect recovery time delay. when fault is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c gives approximately 0.1 ms. 5.13 device status register (addr 0x2d) this read-only register provides fault and thermal-warning status information from the power control block. logic value 1 for faults or warning means normal state. logic 0 means a fault or warning detected on power bridge. the pllul = 1 means that the pll is not locked. 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011 d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault ovfault ocfault ocwarn tfault twarn
STA335W register description 35/43 5.13.1 extended soft vo lume configuration regi sters (addr 0x37 - 0x38) soft volume update has a fixed rate by default. using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates. it is also possible to independently define the fade-in (volume is increased) and fade-out (volume is decreased) rates according to the desired behavior. when svupe = 1 the fade-in rate is defined by the svup[4:0] bits according to the following formula: fade-in rate = 48 / (n + 1) db/ms where n is the svup[4:0] value. table 49. status register bits bit r/w rst name description 7 r - pllul 0: pll locked 1: pll not locked 6r - fault 0: fault detected on power bridge 1: normal operation 5r - uvfault 0: vccxx internally detected < undervoltage threshold 4r - ovfault 0: vccxx internally detected > overvoltage threshold 3 r - ocfault 0: overcurrent fault detected 2 r - ocwarn 0: overcurrent warning 1r - tfault 0: thermal fault, junction temperature over limit detection 0r - twarn 0: thermal warning, junction temperature is close to the fault condition d7 d6 d5 d4 d3 d2 d1 d0 svupe svup[4] svup[3] svup[2] svup[1] svup[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 svdwe svdw4] svdw[3] svdw[2] svdw[1] svdw[0] 00000000 svupe mode 0 when volume is increased, use the default rate 1 when volume is increased, use the rates defined by svup[4:0] . svdwe mode 0 when volume is decreased, use the default rate 1 when volume is decreased, use the rates defined by svdw[4:0] .
register description STA335W 36/43 when svdwe = 1 the fade-out rate is defined by the svdw[4:0] bits according to the following formula: fade-in rate = 48 / (n + 1) db/ms where n is the svdw[4:0] value.
STA335W application 37/43 6 application 6.1 application scheme for power supplies here in the next figure the typical application scheme for STA335W concerning the power supplies. a particular care has to be devoted to the layout of the pcb. in particular all the decoulpling capacitors have to be put as much as possible closed to the device to limit spikes on all the supplies. figure 9. application scheme for power supplies 6.2 pll filter schematic it is recommended to use the above scheme and values for the pll loop filter to achieve the best performances from the device in general application. please be noted that the ground of this filter scheme has to be connected to the ground of the pll without any resistive path. concerning the component values, please take into account that the greater is the filter bandwidth, the less is the lock time but the higher is the pll output jitter. 6.3 typical output configuration here after the typical output configuration used for btl stereo mode. please refer to the application note for all the other possible output configuration recommended schematics.
application STA335W 38/43 figure 10. output configuration for stereo btl mode 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2
STA335W package thermal characteristics 39/43 7 package thermal characteristics using a double-layer pcb the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm 2 and with 16 via holes (see figure 11 ) is 24 c/w in natural air convection. the dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. thus, the maximum estimated dissipated power for the STA335W is: figure 11. double-layer pcb with 2 copper ground areas and 16 via holes figure 12 shows the power derating curve for the powersso-36 package on pcbs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 12. powersso-36 power derating curve 2 x 20 w @ 8 , 18 v pd max ~ 4 w 2 x 10 w + 1 x 20 w @ 4 , 8 , 18 v pd max < 5 w 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes STA335W psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes copper area 2x2 cm and via holes STA335W psso36 STA335W psso36 copper area 3x3 cm and via holes copper area 3x3 cm and via holes
package information STA335W 40/43 8 package information figure 13 shows the package outline and ta bl e 5 0 gives the dimensions. figure 13. powersso-36 slug down outline drawing h x 45
STA335W package information 41/43 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. table 50. powersso-36 slug down dimensions symbol mm inch min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 e3 - 8.5 - - 0.335 f - 2.3 - - 0.091 g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 0.413 h- - 0.40 0.016 k 0 - 8 degrees 8 degrees l 0.60 - 1.00 0.024 0.039 m - 4.30 - 0.169 n - - 10 degrees 10 degrees o - 1.20 - 0.047 q - 0.80 - 0.031 s - 2.90 - 0.114 t - 3.65 - 0.144 u - 1.00 - 0.039 x 4.10 4.70 0.161 0.185 y 4.90 7.10 0.193 0.280
revision history STA335W 42/43 9 revision history table 51. document revision history date revision changes 03-july-2009 1 initial release
STA335W 43/43 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STA335W

	To Download STA335W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .